Configure PIC24E to run at 70 MIPS

Since Microchip introduced their PIC24EP family of products, it took a while before they became available from major vendors in Thailand. This family (and its close relatives dsPIC33EP) is attractive for its 70 MIPS performance. It could not run at that speed right out of the package, considering a user’s choice of setup (such as oscillator type and frequency). So in this brief article, we show an example on how to configure PIC24EP to 70 MIPS. A PIC24EP256MC202 is used on our prototype, with 2 clock choices: the 7.37 MHz on-chip Internal Fast RC (FRC) oscillator, and an external 8 MHz crystal.
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An Introduction to Finite State Machine Design

Roughly speaking, a synchronous Finite State Machine (FSM) refers to a digital circuit/system that has memory, and is driven by a clock signal to change from one state to another depending on the applied input and its previous state. This classification covers from the simplest circuit consisting of only one D flip-flop, to a high-performance computer system. One might refer to FSM as a sequential circuit, in contrast to a combinational circuit that is memoryless. With latest electronics/computer technology, an FSM of low to medium complexity can be designed and implemented rather easily using CPLD/FPGA and software tools. The main advantages of this approach are flexibility, compactness, and ease of maintenance. Hardwiring TTL/CMOS logic gate and DFF ICs together on a PCB is now considered outdated.

Previously on this website, we discussed some design and implementation of quadrature encoder interface circuits (see, for example, VHDL code for quadrature encoder receiver module and reference therein). That is an example of FSM which I normally use in my embedded system classes. I have found, however, that the circuit is somewhat too complicated to beginners who do not have enough background from a basic digital system course. So the purpose of this article is to provide a more simple example and hopefully help students grab the essence of two common approaches for FSM design: the State Diagram , and Algorithmic State Machine (ASM)
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VHDL code for quadrature encoder receiver module

Original document: Quadrature Encoder Receiver Module: An Implementation on FPGA

In the original document cited above, we discussed some designs of quadrature encoder receiver module where Verilog code listings were included. This supplementary article provides the same implementations using VHDL. The development flows remain the same for both design A and B, so we basically list the codes and show simulation results here without repeating the design details.

Design A

For Design A, the receiver module generates pulses at output pin U (up) or D (down), corresponding to whether A leads B, or A lags B, respectively (*). We showed the design process using STG (State Transition Graph) that yielded the results in equation (1) – (4) . The VHDL code for this implementation is in Listing 1 with simulation result shown in Figure 1. (The synthesis and behavioral simulation was performed using Xilinx Webpack 13.4 and Isim simulation, which could be downloaded from Xilinx website.

(*) It turns out that in the original document, the Karnaugh map for output U and D shuffles, so as the resulting equations (3) and (4). You could verify from the simulation in Figure 9. If this gives the wrong sense for your motor setup, simply switch equation (3) and (4). We do so in the VHDL code below.

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Quadrature Encoder Receiver Module: An Implementation on FPGA

In this document we discuss the design and implementation of quadrature encoder receiver module on FPGA using Verilog. The unit receives the A and B pulses that are 90 degree out of phase and generates the up and down pulses depending on whether A leads B, or vice versa. The output pulses give 4 times resolution of the encoder lines. It has been verified by simulation and tested on Xilinx Spartan 3.

Quadrature Encoder Receiver Module: An Implementation on FPGA (.PDF)

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