Quadrature Encoder Receiver Module: An Implementation on FPGA

In this document we discuss the design and implementation of quadrature encoder receiver module on FPGA using Verilog. The unit receives the A and B pulses that are 90 degree out of phase and generates the up and down pulses depending on whether A leads B, or vice versa. The output pulses give 4 times resolution of the encoder lines. It has been verified by simulation and tested on Xilinx Spartan 3.

Quadrature Encoder Receiver Module: An Implementation on FPGA (.PDF)

Servomotor and Encoder Fundamentals

There are many sources that explain servomotor and incremental encoder operations. Here we briefly describe only the essence. Servomotors come in many types, from some simplest brushed DC (Figure 1) preferred by hobbyists, to some sophisticated, high-performance AC brushless servos used in industrial CNCs and robots(Figure 2).

Figure 1: Brushed DC servomotors (Yasakawa Minertia Series)

Figure 2 AC Servomotors and drives (Panasonic)

Assuming the servo systems operated in velocity mode, when you send in analog signals within + 10 V range, the motors rotate with speeds corresponding to the applied input voltages. The incremental encoders generate the quadrature A,B, and index Z signals with frequencies related to the RPMs of motors. As shown in Figure 3, the encoder disk has slots that pass the light beams from LEDs to receiving devices. This generates 3 main signals A, B, and Z. A and B are called quadrature because they have 90 degree phase differences. When the motor turns one direction, say, clockwise, the signal A leads B 90 degree. When it turns counter-clockwise, B leads A 90 degree. With this construction we could construct a circuit that detects the direction of rotation, in addition to the shaft position and speed. The overall encoder receiver unit is shown in Figure 4.

Figure 3: incremental encoder and quadrature signals

In real industrial environment things are not perfect. There are evils such as noise that contaminates the signal. So the signals A, B, Z are sent with their complements A/, B/, and Z/ that are 180 degree out of phase. When noise gets into these signals, the noise component in each signal tends to be similar, so when passed through differential amps the noise are rejected. This is called RS-422 standards. This is the duty of the leftmost block in Figure 4.

After that, the signals pass through another noise rejection unit known as a digital filter, before going to the decoder unit that generates the up/down pulses. The last section is the counter that accumulates the pulses. The content in this counter represents the position of a machine that has long linear movement, for example, an axis of a CNC milling machine.

In this article, we discuss only the digital filter and the x4 decoder in Figure 4.

Figure 4: Overall encoder receiver unit

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Quadrature Encoder Receiver Module: An Implementation on FPGA (.PDF)



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